1. Field of Invention
The present invention relates to a fast methodology and a system for automatically characterizing the setup/hold time for analog IPs based on partial path extraction.
2. Description of Related Art
When given an IP, the IP user would like to have the timing constraint before reaching the first level of DFF (D flip-flop), i.e., the earliest (setup time) and latest (hold time) signal arrival requirement while the timing constraint from the second or deeper levels of DFF is of no concern.
FIG. 1 shows the input pins and a clock pin to the various levels of DFF for an analog IP. Incorrect setup/hold time may cause problems of data synchronization. Besides, characterizing the setup/hold time for entire IPs is inefficient. It takes days/weeks/months to run entire IP characterization.
It needs a generic methodology and system to simplify the input parameter setup while cutting the run time.